Field of the Invention
The present invention relates to a semiconductor circuit configuration and to an associated fabrication method and, in particular to a FLASH EPROM (erasable programmable memory) with a SNOR (selective NOR) architecture in which respective source and drain lines can be driven selectively.
In order to store relatively large volumes of data, magnetic disk drives are generally used at the present time by computer units or computers. However, such disk drives require a relatively large space and have a multiplicity of moving parts. Consequently, they are susceptible to disturbance and have a considerable current consumption. What is more, future computer units or computers and other digital devices such as, for example, digital cameras, music reproduction devices or palm devices or videos will become smaller and smaller, for which reason conventional mechanical storage devices are unsuitable.
As an alternative to such conventional mechanical storage devices, nonvolatile semiconductor memory devices have recently gained increasing acceptance. Such nonvolatile semiconductor memory devices are for example, FLASH memories, E2PROM (electrically erasable programmable memory), EPROM and the like. The so-called NAND and NOR semiconductor memory devices are known as the most important representatives of such electrically erasable and electrically programmable memory devices. In both semiconductor memory devices, the memory cells have so-called one-transistor memory cells, and it is usually the case that a drain region and a source region are formed in an active region of a semiconductor substrate and an insulated charge-storing layer is situated above the channel section lying in between.
While a multiplicity of switching elements are connected to one another in series and are driven via a common selection gate or a selection transistor in NAND semiconductor circuit configurations, the respective switching elements are organized in parallel or in a matrix-type fashion in NOR semiconductor circuit configurations, as a result of which each switching element can be selected individually.
FIG. 1 shows a simplified illustration of a conventional SNOR semiconductor circuit configuration (selective NOR), in which, in contrast to the NOR semiconductor circuit configuration with a xe2x80x9ccommon sourcexe2x80x9d architecture, the individual switching elements (T1, T2, . . . ) are driven selectively via a respective source line SL1, SL2, . . . and via a respective drain line (DL1, DL2, . . . ). This selective driving is carried out, for example, by using respective bit line controllers BLC which, as it were, realize the common bit lines BL1, BL2, . . . In this way, it is possible to carry out further xe2x80x9cshrinksxe2x80x9d or a more extensive integration of the semiconductor circuit configuration since the SNOR architecture does not rely on a predetermined minimum cell transistor length or channel length.
FIG. 2 shows a simplified illustration of a conventional layout of the SNOR semiconductor circuit configuration in accordance with FIG. 1. In accordance with FIG. 2, the switching elements T1, T2, . . . are formed in active regions AA of a semiconductor substrate which have an essentially straight strip-type structure. On the multiplicity of strip-type active regions AA arranged column by column, there are superposed row by row layer stacks that are likewise formed in strip-type fashion. A topmost layer constitutes a control layer or word line WL1 to WL3 of the switching elements T1, T2, . . . Each crossover point or overlap region of such a strip-type active region AA with a word line WL1 to WL3 formed in strip-type fashion thus constitutes a multiplicity of switching elements T. The contact connection of respective drain regions D and source regions S requires contacts K, which are usually formed in the active region AA, but may often also extend into an adjoining isolation region STI (shallow trench isolation). The source lines SL1, SL2, . . . and also the drain lines DL1, DL2, . . . for the respective bit lines BL are then situated in a further overlying layer, which preferably constitutes a first metalization layer. In this case, the drain lines are connected via corresponding contacts K to the associated drain regions D of the active region. The source lines SL1 are connected in the same way via corresponding contacts to the associated source regions.
What is disadvantageous, however, in the case of such a conventional layout is that a more than twice as intensive metalization is present on account of the additional source lines in comparison with a xe2x80x9ccommon sourcexe2x80x9d architecture that represents a limiting factor for more extensive integration or further shrinks. What is more, so-called lithography artifacts are produced particularly in the case of source and drain lines configured in a meandering fashion, which artifacts can lead to a tapering through to interruptions of the respective lines.
In accordance with a further semiconductor circuit configuration (not illustrated), the active regions AA may also have so-called lugs or projections, as a result of which it is possible to alleviate the layout requirements for the source and drain lines. However, since a projection or a lug now has to be formed in the active region, problems once again arise in this region particularly during the lithographic realization.
It is accordingly an object of the invention to provide a semiconductor circuit configuration and also an associated fabrication method, which overcomes the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide a semiconductor circuit configuration and also an associated fabrication method in which a further integration can be realized in a simple manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor circuit configuration including: a having a matrix of a plurality of switching elements; a plurality of essentially straight word lines for row by row driving the plurality of switching elements; a plurality of essentially straight bit lines for column by column driving the plurality of switching elements; and a plurality of electrically conductive connection elements located between the plurality of word lines. The plurality of switching elements have control layers essentially forming the plurality of word lines. The semiconductor substrate includes a plurality of essentially straight active regions. Each one of the plurality of switching elements includes a source region and a drain region spaced apart from the source region. The plurality of the active regions having the source region and the drain region of the plurality of switching elements formed therein. Each one of the plurality of bit lines has a source line for selectively driving the source region of a respective one of the plurality of switching elements. Each one of the plurality of bit lines has a drain line for selectively driving the drain region of a respective one of the plurality of switching elements. Some of the plurality of electrically conductive connection elements are for connecting the source regions of the plurality of switching elements to the source lines the plurality of bit lines. Some of the plurality of electrically conductive connection elements are for connecting the drain regions of the plurality of switching elements to the drain lines of the plurality of bit lines. The plurality of electrically conductive connection elements are formed by a plurality of connection strips. The semiconductor substrate has a surface and a plurality of trench isolations. Each one of the plurality of connection strips includes a portion directly making contact with the source region of a respective one of the plurality of switching elements at the surface of the semiconductor substrate or with the drain region of a respective one of the plurality of switching elements at the surface of the semiconductor substrate. Each one of the plurality of connection strips includes a remaining portion lying above one of the plurality of trench isolations.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a semiconductor circuit configuration. The method includes: forming essentially straight active regions in a semiconductor substrate; forming a first insulating layer and a charge-storing layer; patterning the charge-storing layer; forming a second insulating layer, a first conductive layer, and a protective layer; forming essentially straight word line stacks by patterning the protective layer, the first conductive layer, the second insulating layer and the charge-storing layer; forming source regions and drain regions in the active regions of the semiconductor substrate; forming spacers on sidewalls of the word line stacks and removing portions of the first insulating layer that are not covered; forming a second conductive layer; uncovering the protective layer by reshaping the second conductive layer; forming individual connection strips by patterning the second conductive layer; forming a third insulating layer and source/drain contacts situated therein; and forming essentially straight source lines and essentially straight drain lines.
In particular as a result of using a multiplicity of electrically conductive connection strips for connecting the source and drain regions to the respective source lines and drain lines, and configuring the connection strips to be located between the word lines and directly making contact with the source and drain regions at the surface of the semiconductor substrate, an optimum layout results. This optimum layout is, namely an essentially rectilinear strip structure, and results both for the active region and for the source and drain lines, which makes it possible to prevent problems during the lithography. Furthermore, since the connection strips are formed by deposition and back formation directly between the word lines, a more extensive miniaturization of the cell area for a switching element is obtained.
The connection strip preferably has an in-situ-doped polysilicon, as a result of which a particularly good contact connection of the source and drain regions can be realized and the interspaces between the word lines are optimally filled on account of the outstanding filling properties.
Furthermore, the connection strips may have a siliconized polysilicon, as a result of which the conductivity is improved further and the access times to the switching element are improved further.
A nonvolatile one-transistor memory cell is preferably used as the switching element, as a result of which a nonvolatile memory with a maximum integration density is obtained.
The word lines preferably have an insulating protective layer, which acts as an etching stop layer and as a CMP (chemical mechanical polishing) detection layer, as a result of which a back formation of the connection strip layer, which is initially deposited over the whole area, can be effected in a very exact manner. The protective layer used is, by way of example, a silicon nitride which fulfills the functions as etching stop layer and CMP detection layer.
The essentially straight active regions are preferably formed by using shallow trench isolation in the semiconductor substrate, as a result of which a reliable isolation between the individual switching elements can be realized even with very small feature sizes.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor circuit configuration and associated fabrication method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.